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Workshop Session #1
Time: Monday 8:00 am
Title: Advanced Packaging and Heterogeneous Integration Technologies: Motivation, Trends, and Opportunities
 

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​Speaker: Muhannad Bakir

 

Affiliation: Georgia Tech University

 

Abstract: 

In recent years, the field of advanced packaging has taken center stage as the semiconductor industry pursues ever more energy efficient, high-performance, and low-cost electronic systems. While the field of advanced packaging is undergoing revolutionary technology advances today, there is little doubt that advanced packaging in the new era of Moore’s Law will offer extreme levels of die integration/bonding and begin to blur the boundary between on- and off-chip connectivity due to ever denser physical I/O interfaces/bonds. First, we present the motivations to chiplet based architectures and design considerations. Next, we present a survey of recent advanced packaging technologies covering 2.5D and 3D technologies. Further, emerging HI technologies based on glass-core packaging and their motivation will also be discussed, including for RF/mm-wave applications. Thermal considerations for emerging packaging technologies will also be presented.​​​

Workshop Session #2
Time: Monday 9:00 am
Title: Overview of Phased Array Antenna Systems and Practical Design Considerations

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​Speaker: Daniel Ramirez

 

Affiliation: L3/Harris

 

Abstract: 

Phased array antenna systems are becoming more ubiquitous as fabrication costs decrease, with applications spanning from government to commercial. The desire for multiple functions on single arrays and higher data rates drives many applications to require wideband systems, leading to increased challenges in design. In this talk, we will provide an overview of phased array antenna systems and discuss some key applications which drive the need for wideband capabilities. We will then present a few of the major challenges in phased antenna array system design, such as sizing of an array, time delay architecting, and properly tracking non-linear products.​​​

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Workshop Session #3


Time: Tuesday 1:10 pm
Title: Cadence Workshop

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​Speaker: David Vye

 

Affiliation: Product Management Director, Cadence

 

Abstract:

Combining different types of semiconductors into a single system allows size and power reduction while providing higher performance RF, photonics, and wired interfaces. Integrating chiplets allows circuits to be implemented with individual but optimal processes, leading to overall reduced cost and faster time to market. The Cadence Virtuoso Heterogeneous Integration (HI) workflow allows designers to meet heterogeneous design challenges, such as multi-fabric co-analysis of electrical, electromagnetic (EM), RF and photonic signals, as well as system-level integration and verification, including power and thermal analysis. This workshop presents the latest advances in multi-fabric design, analysis and manufacturing verification with a particular focus on working with RF IP including III-V and Si MMICs, RFICs and laminates.

Moving from chips to chiplets using Virtuoso Heterogenous Integration flow: 

  • Assembly of multiple dies, packages and interposers in a single cockpit 

  • Package DRC and System LVS

  • Die and System level Electromagnetic Analysis

 
Introducing Virtuoso Studio RF for Si MMIC design and analysis: 

  • Introduction to new platform for RF analysis of Virtuoso IP 

  • RF device/circuit characterization with measurement-based simulations

  • Design Si MMIC IP with a RF/mw physical design workflow and Virtuoso PDKs

  • Co-design off-chip RF laminate with embedded Virtuoso IP

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